The present invention relates to a hardware implementation of sorting algorithms, and more specifically, to a tunable hardware sort engine for performing composite sorting algorithms.
Sorting is generally acknowledged to be one of the most time-consuming computer-implemented procedures. It has been estimated that over twenty-five percent of all computer running time is devoted to sorting. In fact, many computing systems use over half of their available computer time for sorting. Numerous proposals and improvements have been disclosed in the art for the purposes of reducing sorting time and increasing sorting efficiency.
Specialized hardware devices, generally referred to as accelerators, are commonly used to perform sorting functions. Currently, such devices are configured to efficiently perform a specific sorting function that has specific performance characteristics, such as sort size and throughput. Accordingly, in order for an accelerator to be used to perform sorting functions with different performance characteristics the accelerator must be re-configured. Deciding and defining the parameters necessary for a sort function in an accelerator typically results in re-architecting the actual sort function, which can be costly from time and implementation effort point of view and limits the amount of design reuse.